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1 dual and quad micropower chopper stabilized, rrio operational amplifiers isl28233, isl28433 the isl28233 and isl28433 are dual and quad micropower, chopper stabilized operational amplifiers that are optimized for single and dual supply operation from 1.8v to 6.0v and 0.825v to 3.0v. their low supply current of 18a and wide input range enable the isl28233, isl28433 to be excellent general purpose op amps for a wide range of applications. the isl28233 and isl28433 are ideal for handheld devices that operate off 2 aa or single li-ion batteries. the isl28233 is available in 8 ld msop, 8 ld soic and 8 ld dfn packages. the isl28433 is available in 14 ld tssop, 14 ld soic and 14 ld 3mmx4mm tdfn packages. all devices operate over the temperature range of -40c to +125c. related literature ?see an1596 , ?isl28233soiceval1z evaluation board user?s guide? ?see an1575 , ?isl28433soiceval1z, ISL28433TSSOPEVAL1Z evaluation board user?s guide? features ? low input offset voltage . . . . . . . . . . . . . . . . . . . . . . 6v, max. ? low offset drift . . . . . . . . . . . . . . . . . . . . . . . 0.05v/c, max. ? quiescent current (per amplifier) . . . . . . . . . . . . . .18a, typ. ? single supply range . . . . . . . . . . . . . . . . . . . . .+1.8v to +6.0v ? dual supply range. . . . . . . . . . . . . . . . . . . . 0.825v to 3.0v ? low noise (0.01hz to 10hz) . . . . . . . . . . . . . . . . . 1.0v p-p , typ. ? rail-to-rail inputs and output ? input bias current . . . . . . . . . . . . . . . . . . . . . . . . .180pa, max. ? operating temperature range . . . . . . . . . . . .-40c to +125c applications ? bi-directional current sense ? temperature measurement ?medical equipment ? electronic weigh scales ? precision/strain gauge sensor ? precision regulation ?low ohmic current sense ? high gain analog front ends typical application v os vs temperature bi-directional current sense amplifier i-sense+ 0.1 4.99k 4.99k 499k 499k + - v+ v- gnd v sense out v ref v + +1.8v to +6.0v i-sense- temperature (c) input offset voltage (v) -4 -3 -2 -1 0 1 2 3 4 -50 -25 0 25 50 75 100 125 july 26, 2011 fn7692.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl28233, isl28433 2 fn7692.3 july 26, 2011 ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # isl28233fuz 233fz 8 ld msop m8.118a isl28233frz 233z 8 ld 3mmx3mm dfn l8.3x3j isl28233fbz 28233 fbz 8 ld soic m8.15e isl28433fbz 28433 fbz 14 ld soic mdp0027 isl28433fvz 28433 fvz 14 ld tssop mdp0044 coming soon isl28433frtz tbd 14 ld 3x4 mm tdfn tbd isl28233soiceval1z evaluation board ISL28433TSSOPEVAL1Z evaluation board isl28433soiceval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requir ements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl28233 , isl28433 . for more information on msl please see techbrief tb363 .
isl28233, isl28433 3 fn7692.3 july 26, 2011 pin configurations isl28233 (8 ld msop, soic) top view isl28233 (8 ld dfn) top view isl28433 (14 ld soic) top view isl28433 (14 ld tdfn) top view isl28433 (14 ld tssop) top view 1 2 3 4 8 7 6 5 out_a in-_a in+_a v+ out_b in-_b v- in+_b + - +- out_a in-_a in+_a v+ out_b in-_b v- in+_b 2 3 4 1 7 6 5 8 out_a in-_a in+_a v+ in+_b in-_b out_b out_d in-_d in+_d v- in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - +- + - +- out_a in-_a in+_a v+ in+_b in-_b out_b out_d in-_d in+_d v- in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - +- + - +- out_a in-_a in+_a v+ in+_b in-_b out_b out_d in-_d in+_d v- in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - +- + - +-
isl28233, isl28433 4 fn7692.3 july 26, 2011 pin descriptions isl28233 (8 ld msop, soic, dfn) isl28433 (14 ld tssop, soic, tdfn) pin name function equivalent circuit 3 3 in+_a non-inverting input circuit 1 5 5 in+_b -10in+_c -12in+_d 4 11 v- negative supply 22in-_ainverting input (see circuit 1) 66in-_b -9in-_c -13in-_d 11out_aoutput circuit 2 77out_b -8out_c -14out_d 8 4 v+ positive supply - - pad thermal pad thermal pad. connect to most negative supply. tdfn and dfn packages only. in- v+ in+ v- + - + - clock gen + drivers v + v- out
isl28233, isl28433 5 fn7692.3 july 26, 2011 absolute maximum rating s thermal information max supply voltage v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5v max voltage vin to gnd . . . . . . . . . . . . . . . . . . . . (v- - 0.3v) to (v+ + 0.3v)v max input differential voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v max input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma max voltage vout to gnd (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0v esd tolerance human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 4000v machine model (tested per jesd22-a115b) . . . . . . . . . . . . . . . . . . 400v charged device model (tested per jesd22-c110d) . . . . . . . . . . . 2000v latch-up (tested per jesd78b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c thermal resistance (typical) ja (c/w) jc (c/w) 14 ld tssop (notes 4, 7) . . . . . . . . . . . . . . 110 40 14 ld soic (notes 4, 7) . . . . . . . . . . . . . . . . 75 47 14 ld tdfn (notes 5, 6) . . . . . . . . . . . . . . . tbd tbd 8 ld msop (notes 4, 7) . . . . . . . . . . . . . . . . 180 65 8 ld soic (notes 4, 7) . . . . . . . . . . . . . . . . . 125 90 8 ld dfn (notes 5, 6). . . . . . . . . . . . . . . . . . 53 12 maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for jc , the ?case temp? location is taken at the package top center. electrical specifications v+ = 5v, v- = 0v, v cm = 2.5v, t a = +25c, r l = 10k ? , unless otherwise specified. boldface limits apply over the operating temperature range,-40c to +125c. parameter description conditions min (note 8) typ max (note 8) unit dc specifications v os input offset voltage -6 2 6 v t = -40c to +125c -11 - 11 v tcv os input offset voltage temperature coefficient t = -40c to +125c -0.05 0.01 0.05 v/c i os input offset current -10- pa tci os input offset current temperature coefficient t = -40c to +85c - 0.11 - pa/c i b input bias current t = -40c to +85c -180 - 180 pa t = -40c to +125c -600 - 600 pa tci b input bias current temperature coefficient t = -40c to +85c - 0.49 - pa/c cmir v+ = 5.0v, v- = 0v guaranteed by cmrr -0.1 - 5.1 v cmrr common mode rejection ratio vcm = -0.1v to 5.1v 118 125 - db 115 -- db psrr power supply rejection ratio vs = 1.8v to 6.0v 110 138 - db 110 -- db v oh output voltage, high 4.965 4.981 - v v ol output voltage, low -18 35 mv a ol open loop gain r l = 1m -174- db v+ supply voltage guaranteed by psrr 1.8 - 6.0 v i s supply current, per amplifier r l = open - 18 25 a -- 35 a
isl28233, isl28433 6 fn7692.3 july 26, 2011 i sc+ output source short circuit current r l = short to v- 13 17 26 ma i sc- output sink short circuit current r l = short to v+ -26 -19 -13 ma ac specifications gbwp gain bandwidth product a v = 100, r f = 100k , r g =1k , r l = 10k to v cm - 400 - khz e n v p-p peak-to-peak input noise voltage f = 0.01hz to 10hz - 1.0 - v p-p e n input noise voltage density f = 1khz - 65 - nv/ (hz) i n input noise current density f = 1khz - 72 - fa/ (hz) f = 10hz - 79 - fa/ (hz) c in differential input capacitance f = 1mhz - 1.6 - pf common mode input capacitance - 1.12 - pf transient response sr positive slew rate v out = 1v to 4v, r l = 10k -0.2- v/s negative slew rate -0.1- v/s t r , t f , small signal rise time, t r 10% to 90% a v = +1, v out = 0.1v p-p , r f = 0 , r l = 10k , c l =1.2pf -1.1- s fall time, t f 10% to 90% - 1.1 - s t r , t f large signal rise time, t r 10% to 90% a v = +1, v out = 2v p-p , r f =0 , r l = 10k , c l =1.2pf -20- s fall time, t f 10% to 90% - 30 - s t s settling time to 0.1%, 2v p-p step a v = +1, r f = 0 , r l =10k , c l = 1.2pf -35- s t recover output overload recovery time, recovery to 90% of output saturation a v = +2, r f = 10k , r l =open , c l = 3.7pf - 10.5 - s note: 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications v+ = 5v, v- = 0v, v cm = 2.5v, t a = +25c, r l = 10k ? , unless otherwise specified. boldface limits apply over the operating temperature range,-40c to +125c. (continued) parameter description conditions min (note 8) typ max (note 8) unit
isl28233, isl28433 7 fn7692.3 july 26, 2011 n typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. figure 1. v os vs supply voltage figure 2. v os vs temperature figure 3. v os vs temperature figure 4. i b+ vs temperature figure 5. i b- vs temperature figure 6. i os vs temperature supply voltage (v) input offset voltage (v) -4 -3 -2 -1 0 1 2 3 4 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 temperature (c) input offset voltage (v) -4 -3 -2 -1 0 1 2 3 4 -50 -25 0 25 50 75 100 125 v s = 0.825v v in = 0v r l = open temperature (c) input offset voltage (v) -4 -3 -2 -1 0 1 2 3 4 -50 -25 0 25 50 75 100 125 v s = 2.5v v in = 0v r l = open temperature (c) input bias current (pa) -100 0 100 200 300 400 -50 -25 0 25 50 75 100 125 v s = 2.5v v s = 0.825v temperature (c) input bias current (pa) 0 100 200 300 400 -50 -25 0 25 50 75 100 125 -100 v s = 2.5v v s = 0.825v temperature (c) input offset current (pa) -150 -100 -50 0 50 100 -50 -25 0 25 50 75 100 125 v s = 2.5v v s = 0.825v
isl28233, isl28433 8 fn7692.3 july 26, 2011 figure 7. supply current vs temperature figure 8. input noise voltage 0.01hz to 10hz figure 9. input noise voltage density vs frequency f igure 10. input noise current density vs frequency figure 11. frequency response vs open loop gain, r l = 10k ? figure 12. frequency response vs open loop gain, r l = 10m ? typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) temperature (c) supply current (a) 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125 v s = 2.5v per amplifier v s = 0.825v -1000 -800 -600 -400 -200 0 200 400 600 800 1000 20 30 40 50 60 70 80 90 100 peak to peak noise voltage (nv) 0.1 10 v s = 5v r l = 100k a v = 10,000 c l = 3.7pf rg = 10, rf = 100k time (s) frequency (hz) 10 100 1000 input noise voltage (nv/ hz) 0.001 0.01 0.1 1 10 100 1k 10k 100k v s = 5v a v = 1 frequency (hz) 0.01 0.1 1.0 0.001 0.01 0.1 1 10 100 1k 10k 100k input noise current (pa/ hz) v s = 5v a v = 1 -100 -50 0 50 100 150 200 1 100 10k 100k 1m 10m open loop gain (db)/phase () frequency (hz) r l = 10k simulation c l = 100pf gain phase 1k 10 100m 10m 1m 0.1m -100 -50 0 50 100 150 200 open loop gain (db)/phase () frequency (hz) r l = 10m simulation c l = 100pf gain phase 1 100 10k 100k 1m 10m 1k 10 100m 10m 1m 0.1m
isl28233, isl28433 9 fn7692.3 july 26, 2011 figure 13. gain vs frequency vs r l , v s = 0.8v figure 14. gain vs frequency vs r l , v s = 2.5v figure 15. gain vs frequency vs feedback resistor values r f /r g figure 16. gain vs frequency vs v out, r l = open figure 17. frequency response vs closed loop gain figure 18. gain vs frequency vs supply voltage typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 1k 10k 100k 1m 10m frequency (hz) normalized gain (db) r l = 10k r l = 49.9k r l = open r l = 1k r l = 100k v s = 0.8v a v = +1 v out = 10mv p-p c l = 3.7pf frequency (hz) normalized gain (db) 100 1k 10k 100k 1m 10m -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 r l = 100k r l = open r l = 1k v s = 2.5v a v = +1 v out = 10mv p-p c l = 3.7pf r l = 49.9k r l = 10k 1 2 3 4 5 6 7 8 9 10 frequency (hz) gain (db) 100 1k 10k 100k 1m 10m 0 v s = 2.5v r l = 100k a v = +2 v out = 10mv p-p c l = 3.7pf rf = rg = 100k rf = rg = 10k rf = rg = 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 100 1k 10k 100k 1m 10m v out = 100mv v out = 1v v out = 500mv v out = 250mv v out = 10mv v s = 2.5v r l = open a v = 1 c l = 3.7pf -10 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 10m frequency (hz) gain (db) a v = 1 a v = 10 a v = 100 a v = 1000 v+ = 5v v out = 10mv p-p c l = 3.7pf r l = 100k rg = 10k, rf = 100k rg = 100, rf = 100k rg = 1k, rf = 100k rg = open, rf = 0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 100 1k 10k 100k 1m 10m r l = 100k a v = +1 v out = 10mv p-p c l = 3.7pf v s = 0.8v v s = 1.5v v s = 0.7v v s = 2.75v
isl28233, isl28433 10 fn7692.3 july 26, 2011 figure 19. gain vs frequency vs c l figure 20. cmrr vs frequency, v s = 2.5v figure 21. psrr vs frequency, v s = 0.8v figure 22. psrr vs frequency, v s = 2.5v figure 23. cmrr vs temperature figure 24. psrr vs temperature typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) -10 -8 -6 -4 -2 0 2 4 6 8 frequency (hz) normalized gain (db) 100 1k 10k 100k 1m 10m c l = 824pf c l = 224pf c l = 474pf c l = 51pf c l = 3.7pf c l = 104pf v s = 2.5v r l = 100k a v = +1 v out = 10mv p-p -140 -120 -100 -80 -60 -40 -20 0 20 frequency (hz) cmrr (db) 100 1k 10k 100k 1m 10m v s = 2.5v r l = 100k a v = +1 v cm = 1v p-p simulation -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (hz) psrr (db) 100 1k 10k 100k 1m 10m v s = 0.8v r l = 100k a v = +1 v cm = 1v p-p c l = 16.3pf psrr+ 10 psrr- -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (hz) psrr (db) 100 1k 10k 100k 1m 10m psrr- psrr+ v s = 2.5v r l = 100k a v = +1 v cm = 1v p-p c l = 16.3pf 10 temperature (c) cmrr (db) 130 135 140 145 150 155 -50 -25 0 25 50 75 100 125 v s = 2.5v v cm = 2.6v temperature (c) psrr (db) 100 110 120 130 140 150 160 -50 -25 0 25 50 75 100 125 v s = 1.8v to 6.0v
isl28233, isl28433 11 fn7692.3 july 26, 2011 figure 25. large signal step response (4v) figure 26. large signal step response (1v) fi gure 27. small signal step response (100mv) figure 28. v oh vs temperature figure 29. v ol vs temperature typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400 time (s) signal (v) r l = 100k a v = 1 v out = 4v p-p c l = 3.7pf 0 0.2 0.4 0.6 0.8 1.0 1.2 0 102030405060708090100 time (s) signal (v) r l = 100k a v = 1 v out = 1v p-p c l = 3.7pf 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0 5 10 15 20 25 30 35 40 time (s) signal (v) r l = 100k a v = 1 v out = 100mv p-p c l = 3.7pf temperature (c) v oh (v) 4.975 4.980 4.985 4.990 4.995 5.000 -50 -25 0 25 50 75 100 125 v s =5v r l = 10k ? 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125 temperature (c) v ol (mv) v s = 5v r l = 10k ?
isl28233, isl28433 12 fn7692.3 july 26, 2011 figure 30. crosstalk vs frequency, v s = 0.8v figure 31. crosstalk vs frequency, v s = 2.5v figure 32. tci os histogram figure 33. tci b histogram figure 34. tcv os histogram figure 35. i os vs v cm typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) -140 -120 -100 -80 -60 -40 -20 1k 10k 100k 1m frequency (hz) crosstalk (db) v s = 0.8v r l = open a v = 1 c l = 3.7pf v out = 1v p-p frequency (hz) crosstalk (db) v s = 2.5v r l = open a v = 1 c l = 3.7pf v out = 1v p-p -140 -120 -100 -80 -60 -40 -20 1k 10k 100k 1m 0 2 4 6 8 10 12 - 0 . 0 4 0 0 . 0 4 0 . 0 8 0 . 1 2 0 . 1 6 0 . 2 0 0 . 2 4 0 . 2 8 0 . 3 2 tci os (pa/c) frequency (units) t a = -40c to +85c 0 2 4 6 8 10 12 14 0 . 4 2 0 . 4 6 0 . 5 0 0 . 5 4 0 . 5 8 0 . 6 2 0 . 6 6 0 . 7 0 tci b (pa/c) frequency (units) t a = -40c to +85c tcv os (nv/c) frequency (units) 0 5 10 15 20 25 30 35 40 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 t a = -40c to +125c common mode voltage (v) input offset current (pa) -40 -30 -20 -10 0 10 20 30 40 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
isl28233, isl28433 13 fn7692.3 july 26, 2011 figure 36. i b+ vs v cm figure 37. i b- vs v cm figure 38. v os vs v cm typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) -20 -10 0 10 20 30 40 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 common mode voltage (v) i b+ bias current (pa) i b- bias current (pa) common mode voltage (v) -20 -15 -10 -5 0 5 10 15 20 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 input offset voltage (v) common mode voltage (v) -6 -4 -2 0 2 4 6 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 figure 39. isl28233, isl28433 functional block diagram v out in- in+ 5khz crossover filter chopper stabilized dc offset correction main amplifier
isl28233, isl28433 14 fn7692.3 july 26, 2011 applications information functional description the isl28233 and isl28433 use a proprietary chopper-stabilized technique (see figure 39) that combines a 400khz main amplifier with a very high open loop gain (174db) chopper amplifier to achieve very low offset voltage and drift (2v, 0.01v/c typical) while co nsuming only 18a of supply current per channel. this multi-path amplifier architec ture contains a time continuous main amplifier whose input dc offset is corrected by a parallel- connected, high gain chopper stabilized dc correction amplifier operating at 100khz. from dc to ~5 khz, both amplifiers are active with dc offset correction and most of the low frequency gain is provided by the chopper amplifier. a 5khz crossover filter cuts off the low frequency amplifier path leaving the main amplifier active out to the 400khz gain-bandwidth product of the device. the key benefits of this architecture for precision applications are very high open loop gain, very low dc offset, and low 1/f noise. the noise is virtually flat across the frequency range from a few millihertz out to 100khz, except for the narrow noise peak at the amplifier crossover frequency (5khz). rail-to-rail input and output (rrio) the rrio cmos amplifier uses para llel input pmos and nmos that enable the inputs to swing 100mv beyond either supply rail. the inverting and non-inverting inputs do not have back-to-back input clamp diodes and are capable of maintaining high input impedance at high differential input voltages . this is effective in eliminating output distortion caused by high slew-rate input signals. the output stage uses common source connected pmos and nmos devices to achieve rail-to-rail output drive capability with 17ma current limit and the capability to swing to within 20mv of either rail while driving a 10k load. in+ and in- protection all input terminals have internal esd protection diodes to both positive and negative supply rail s, limiting the input voltage to within one diode beyond the suppl y rails. for applications where either input is expected to exceed the rails by 0.5v, an external series resistor must be used to ensure the input currents never exceed 20ma (see figure 40). layout guidelines for high impedance inputs to achieve the maximum performance of the high input impedance and low offset voltag e of the isl28233 and isl28433 amplifiers, care should be taken in the circuit board layout. the pc board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. high gain, precision dc-coupled amplifier the circuit in figure 41 implements a single-stage dc-coupled amplifier with an input dc sensitiv ity of under 100nv that is only possible using a low vos amplifier with high open loop gain. high gain dc amplifiers operating from low voltage supplies are not practical using typical low offset precision op amps. for example, a typical precision amplifier in a gain of 10kv/v with a 100v v os and offset drift 0.5v/c of a low offset op amp would produce a dc error of >1v with an additional 5mv/ c of temperature dependent error making it difficult to resolve dc input voltage changes in the mv range. the 6v max v os and 0.05v/ c max temperature drift of the isl28233, isl28433 produces a temperature stable maximum dc output error of only 60mv with a maximum output temperature drift of 0.5mv/c. th e additional benefit of a very low 1/f noise corner frequency and some feedback filtering enables dc voltages and voltage fluctuations well below 100nv to be easily detected with a simple single stage amplifier. isl28233, isl28433 spice model figure 42 shows the spice model schematic and figure 43 shows the net list for the isl28233, isl28433 spice model. the model is a simplified version of the actual device and simulates important parameters such as noise, slew rate, gain and phase. the model uses typical parameters from the ?electrical specifications table? on page 5. the poles and zeroes in the model were determined from the actual open and closed-loop gain and phase response. this enables the model to present an accurate ac representation of the actual device. the model is configured for ambient temperature of +25c. figures 44 through 51 show the characterization vs simulation results for the noise density, frequency response vs close loop gain, gain vs frequency vs c l and large signal step response (4v). license statement the information in this spice model is protected under the united states copyright laws. intersil corporation hereby grants users of this macro-model hereto referred to as ?licensee?, a nonexclusive, nontransferable licence to use this model as long as the licensee abides by the terms of this agreement. before using this macro-model, the licensee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. figure 40. input current limiting - + r in r l v in v out figure 41. high gain, precision dc-coupled amplifier - + 100 r l v in v out 1m 1m , 100 -2.5v +2.5v a cl = 10kv/v c f 0.018f
isl28233, isl28433 15 fn7692.3 july 26, 2011 the licensee may not sell, loan, rent , or license the macro-model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro-model to suit his/her specific applications, and the lice nsee may make copies of this macro-model for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including buy not limited to any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. intersil reserves the right to make changes to the product and the macro-mo del without prior notice.
isl28233, isl28433 16 fn7692.3 july 26, 2011 + - + - i1 i2 m1 m2 r2 r1 r3 r4 en r21 r22 dn1 v15 dn2 v16 cin1 cin2 vin+ vin- 7 13 12 4 7 13 12 4 + - + - + - + - 7 vv3 16 4 + - + - + - + - g2 g1 r6 r5 d1 v3 v4 d2 g4 g3 r8 r7 c1 c2 d3 v5 v6 d4 7 4 16 vv3 + - + - + - + - + - + - e1 g5 g5 r12 r11 l1 r10 r9 l2 g7 g8 r14 r13 c4 c3 g9 g10 d5 d6 d7 d8 g11 g10 r16 r15 v+ vout v- voltage noise input stage gain stage sr limit & first pole pole output stage zero/pole figure 42. spice circuit schematic
isl28233, isl28433 17 fn7692.3 july 26, 2011 v * isl28233, isl28433 macromodel * revision b, april 2009 * ac characteristics, voltage noise *copyright 2009 by intersil corporation *refer to data sheet ?license statement? use of *this model indicates y our acceptance with the *terms and provisions in the license statement. * connections: +input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28233 3 2 7 4 6 * *voltage noise d_dn1 102 101 dn d_dn2 104 103 dn r_r21 0 101 120k r_r22 0 103 120k e_en 8 3 101 103 1 v_v15 102 0 0.1vdc v_v16 104 0 0.1vdc * *input stage c_cin1 8 0 0.4p c_cin2 2 0 2.0p r_r1 9 10 10 r_r2 10 11 10 r_r3 4 12 100 r_r4 4 13 100 m_m1 12 8 9 9 pmosisil + l=50u + w=50u m_m2 13 2 11 11 pmosisil + l=50u + w=50u i_i1 4 7 dc 92ua i_i2 7 10 dc 100ua * *gain stage g_g1 4 vv2 13 12 0.0002 g_g2 7 vv2 13 12 0.0002 r_r5 4 vv2 1.3meg r_r6 vv2 7 1.3meg d_d1 4 14 dx d_d2 15 7 dx v_v3 vv2 14 0.7vdc v_v4 15 vv2 0.7vdc * *sr limit first pole g_g3 4 vv3 vv2 16 1 g_g4 7 vv3 vv2 16 1 r_r7 4 vv3 1meg r_r8 vv3 7 1meg c_c1 vv3 7 12u c_c2 4 vv3 12u d_d3 4 17 dx d_d4 18 7 dx v_v5 vv3 17 0.7vdc v_v6 18 vv3 0.7vdc * *zero/pole e_e1 16 4 7 4 0.5 g_g5 4 vv4 vv3 16 0.000001 g_g6 7 vv4 vv3 16 0.000001 l_l1 20 7 0.3h r_r12 20 7 2.5meg r_r11 vv4 20 1meg l_l2 4 19 0.3h r_r9 4 19 2.5meg r_r10 19 vv4 1meg *pole g_g7 4 vv5 vv4 16 0.000001 g_g8 7 vv5 vv4 16 0.000001 c_c3 vv5 7 0.12p c_c4 4 vv5 0.12p r_r13 4 vv5 1meg r_r14 vv5 7 1meg * *output stage g_g9 21 4 6 vv5 0.0000125 g_g10 22 4 vv5 6 0.0000125 d_d5 4 21 dy d_d6 4 22 dy d_d7 7 21 dx d_d8 7 22 dx r_r15 4 6 8k r_r16 6 7 8k g_g11 6 4 vv5 4 -0.000125 g_g12 7 6 7 vv5 -0.000125 * .model pmosisil pmos (kp=16e-3 vto=10m) .model dn d(kf=6.4e-16 af=1) .model dx d(is=1e-18 rs=1) .model dy d(is=1e-15 bv=50 rs=1) .ends isl28233 figure 43. spice net list
isl28233, isl28433 18 fn7692.3 july 26, 2011 characterization vs simulation results figure 44. characterized input noise voltage density vs frequency figure 45. simulated input noise voltage density vs frequency figure 46. characterized frequency response vs closed loop gain figure 47. simulated frequency response vs closed loop gain figure 48. characterized gain vs frequency vs c l figure 49. simulated gain vs frequency vs c l frequency (hz) 10 100 1000 input noise voltage (nv/ hz 0.001 0.01 0.1 1 10 100 1k 10k 100k v+ = 5v a v = 1 frequency (hz) 10 100 1000 input noise voltage (nv/ hz 0.1 1 10 100 1k 10k 100k v + = 5v a v = 1 -10 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 10m frequency (hz) gain (db) a v = 1 a v = 10 a v = 100 a v = 1000 v + = 5v v out = 10mv p-p c l = 3.7pf r l = 100k r g = 10k, r f = 100k r g = 100, r f = 100k r g = 1k, r f = 100k r g = open, r f = 0 10 100 1k 10k 100k 1m 10m frequency (hz) a v = 1 a v = 10 a v = 100 a v = 1000 rg = 1k, rf = 100k rg = 100, rf = 100k rg = 10m rf = 1 rg = 10k, rf = 100k -10 0 10 20 30 40 50 60 70 gain (db) frequency (hz) normalized gain (db) -10 -8 -6 -4 -2 0 2 4 6 8 10k 100k 1m 10m 1k 100 v+ = 5v r l = 100k a v = +1 v out = 10mvp-p cl = 824pf c l = 224pf c l = 474pf c l = 51pf c l = 3.7pf c l = 104pf c l = 824pf c l = 474pf cl = 224pf c l = 824pf c l = 3.7pf frequency (hz) -10 -8 -6 -4 -2 0 2 4 6 8 10k 100k 1m 10m 1k 100 c l = 224pf normalized gain (db)
isl28233, isl28433 19 fn7692.3 july 26, 2011 figure 50. characterized large signal step response (4v) figure 51. simulated large signal step response (4v) characterization vs simulation results (continued) time (s) large signal (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400 v+ = 5v r l = 100k a v = 1 c l = 3.7pf v out = 4v p-p v out v in time (s) large signal (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400
isl28233, isl28433 20 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7692.3 july 26, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl28233, isl28433 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/31/11 fn7692.3 changed minimum operating supply voltage from +1.65v to +1.8v throughout entire datasheet. 3/24/11 added to ordering information table on page 2 - isl28233soiceval1z, ISL28433TSSOPEVAL1Z, isl28433soiceval1z 12/2/10 fn7692.2 added ?related literature? on page 1 removed "coming soon" from isl28233frz device (8 ld dfn) in "ordering information" on page 2. corrected thermal pad pin name in ?pin descriptions? on page 4 from "nc" to "pad" corrected ja note for tdfn package in ?thermal information? on page 5 from " ja is measured with the component mounted on a high effective thermal conductivi ty test board in free air. see tech brief tb379 for details." to " ja is measured in free air with the component mo unted on a high effective thermal conductivity test board with "direct attach" features. see tech brie f tb379." (since tdfn has thermal pad; tdfn package option not released yet) 10/27/10 fn7692.1 changed part marking for isl28233fuz from 8233z to 233fz in ?ordering information? table on page 2 added isl28233 in dfn package to ordering information? table on page 2. on page 6, removed note 8. changed note in min max columns of ?electrical specifications? table from: ?parameters with min and/or max limits are 100% tested at +25c, un less otherwise specified. temperature limits established by characterizati on and are not production tested.? to: "compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design." 8/25/10 fn7692.0 initial release.
isl28233, isl28433 21 fn7692.3 july 26, 2011 package outline drawing l8.3x3j 8 lead dual flat no-lead plastic package rev 0 9/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view side view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 index area 6x 0.65 1.64 +0.10/ - 0.15 8 1 8x 0.400 0.10 6 max 1.00 see detail "x" 0.08 0.10 c c c ( 2.80 ) (1.64) ( 8 x 0.30) ( 8x 0.60) ( 2.38 ) ( 1.95) 2.38 0.10 8x 0.30 a mc b 4 2x 1.950 +0.10/ - 0.15 (6x 0.65) 4 5 pin 1
isl28233, isl28433 22 fn7692.3 july 26, 2011 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?
isl28233, isl28433 23 fn7692.3 july 26, 2011 package outline drawing m8.118a 8 lead mini small outlin e plastic package (msop) rev 0, 9/09 plastic or metal protrusions of 0.15mm max per side are not dimensions ?d? and ?e1? are measured at datum plane ?h?. this replaces existing drawing # mdp0043 msop 8l. plastic interlead protrusions of 0.25mm max per side are not dimensioning and tolerancing conform to jedec mo-187-aa 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view 1 typical recommended land pattern top view side view 2 included. included. gauge plane 33 0.25 c a b b 0.10 c 0.08 c a b a 0.25 0.55 0.15 0.95 bsc 0.18 0.05 1.10 max c h 4.40 3.00 5.80 0.65 3.00.1 4.90.15 1.40 0.40 0.65 bsc pin# 1 id detail "x" 0.33 +0.07/ -0.08 0.10 0.05 3.00.1 1 2 8 0.860.09 seating plane and amse y14.5m-1994.
isl28233, isl28433 24 fn7692.3 july 26, 2011 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
isl28233, isl28433 25 fn7692.3 july 26, 2011 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994

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